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Dr.-Ing. Tim Baldauf

Fakultät Elektrotechnik
  • Mechanisch verspannte Halbleiter
  • Physik von Halbleiter-Bauelementen
  • Rekonfigurierbare Feld-Effekt-Transistoren (RFET)
  • Skalierung von Ultra-Kurzkanal-Transistoren
  • TCAD-Simulationen

E-Mail: tim.baldauf(at)htw-dresden.de
ResearchGate: https://www.researchgate.net/profile/Tim_Baldauf

1Geleitete Drittmittelprojekte
30Publikationen
  • Vertically Integrated Reconfigurable Silicon Nanowire Transistors
    HEINZIG, André , MIKOLAJICK, Thomas, WEBER, Walter M., 2018. Vertically Integrated Reconfigurable Silicon Nanowire Transistors. IEEE Electron Device Letters, Volume: 39 , Issue: 8 , Aug. 2018. DOI: 10.1109/LED.2018.2847902
  • A wired-AND transistor: Polarity controllable FET with multiple inputs
    MAIK, Simon, TROMMER, Jens, LIANG, B., FISCHER, Dustin, BALDAUF, Tim, KHAN, M.B., HEINZIG, André, KNAUT, Martin, GEORGIEV, Yordan M., ERBE, Artur, BARTHA, Johann Wolfgang , MIKOLAJICK, Thomas, WEBER, Walter M., 2018. A wired-AND transistor: Polarity controllable FET with multiple inputs. 76th Device Research Conference (DRC), 24.06.-27.06.2018, Santa Barbara, USA, IEEE . DOI: 10.1109/DRC.2018.8442159
  • A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs
    RAI, Shubham, RUPANI, Ansh, WALTER, Dennis, RAITZA, Michael, HEINZIG, André, BALDAUF, Tim, TROMMER, Jens, MAYR, Christian Georg, WEBER, Walter M., KUMAR, Akash, 2018. A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs. IEEE. DOI: 10.23919/DATE.2018.8342080
  • In-depth electrical characterization of carrier transport in ambipolar Si-NW Schottky-barrier FETs
    JEON, Dae-Young, BALDAUF, Tim, JEONG PARK, So , PREGI, Sebastian, BARABAN, Larysa, CUNIBERTI, Gianaurelio, MIKOLAJICK, Thomas, WEBER, Walter M., 2017. In-depth electrical characterization of carrier transport in ambipolar Si-NW Schottky-barrier FETs. 47th European Solid-State Device Research Conference (ESSDERC), Leuven, Belgium, 11.09.-14.09.2017. 10.1109/ESSDERC.2017.8066652
  • The RFET-a reconfigurable nanowire transistor and its application to novel electronic circuits and systems
    MIKOLAJICK, Thomas, HEINZIG, André, TROMMER, Jens, BALDAUF, Tim, WEBER, Walter M., 2017. The RFET-a reconfigurable nanowire transistor and its application to novel electronic circuits and systems. Semiconductor Science and Technology, vol. 32(4).
  • Tuning the Tunneling Probability by Mechanical Stress in Schottky Barrier based Reconfigurable Nanowire Transistors
    ANDRé, Heinzig, TROMMER, Jens, MIKOLAJICK, Thomas, WEBER, Walter Michael, 2017. Tuning the Tunneling Probability by Mechanical Stress in Schottky Barrier based Reconfigurable Nanowire Transistors. In: Solid-State Electronics, Volume 128, Pages 148–154. DOI: 10.1016/j.sse.2016.10.009
  • Enabling Energy Efficiency and Polarity-Control in Germanium Nanowire Transistors by Individually Gated Nano-Junctions
    J. Trommer, A. Heinzig, U. Mühle, M. Löffler, A. Winzer, P.M. Jordan, J. Beister, T. Baldauf, M. Geidel, B. Adolphi, E. Zschech, T. Mikolajick und W.M. Weber, 2017. Enabling Energy Efficiency and Polarity-Control in Germanium Nanowire Transistors by Individually Gated Nano-Junctions. ACS nano, vol. 11 (2), pp 1704–1711. DOI: 10.1021/acsnano.6b07531
  • Bringing reconfigurable nanowire FETs to a logic circuits compatible process platform
    SIMON, Maik, HEINZIG, André, TROMMER, Jens, BALDAUF, Tim, MIKOLAJICK, Thomas, WEBER, Walter M., 2016. Bringing reconfigurable nanowire FETs to a logic circuits compatible process platform. Nanotechnology Materials and Devices Conference (NMDC), Toulouse, France, 09.-12.10.2016, pp. 1-3. DOI: 10.1109/NMDC.2016.7777085
  • Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits
    J. Trommer, A. Heinzig, T. Baldauf, T. Mikolajick, W.M. Weber, M. Raitza und M. Völp, 2016. Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits. Conference on Design, Automation & Test in Europe 2016 (pp. 169-174). EDA Consortium. ISBN 978-3-9815-3707-9
  • High-Yield Reconfigurable Silicon and Germanium Nanowire Transistors and Compact Logic Circuits (Invited)
    WEBER, Walter M., HEINZIG, André, TROMMER, Jens, BALDAUF, Tim, RAITZA, Michael, GRUBE, Matthias, PREGL, Sebastian, JEON, Dae-Young, PARK, S.-J., SESSI, Violetta, MIKOLAJICK, Thomas, 2016. High-Yield Reconfigurable Silicon and Germanium Nanowire Transistors and Compact Logic Circuits (Invited). The Electrochemical Society, vol.. 37, pp. 2315-2315.
  • Strain-Engineering for Improved Tunneling in Reconfigurable Silicon Nanowire Transistors
    HEINZIG, André, TROMMER, Jens, MIKOLAJICK, Thomas, WEBER, Walter Michael, 2016. Strain-Engineering for Improved Tunneling in Reconfigurable Silicon Nanowire Transistors. EUROSOI/ULIS 2016, IEEE Xplore Digital Library, Wien, Österreich.
  • Stress Dependent Performance Optimization of Reconfigurable Silicon Nanowire Transistors
    HEINZIG, André, TROMMER, Jens, MIKOLAJICK, Thomas, WEBER, Walter M. , 2015. Stress Dependent Performance Optimization of Reconfigurable Silicon Nanowire Transistors. IEEE Electron Device Letters, vol. 36 (10), pp. 991-993. DOI: 10.1109/LED.2015.2471103
  • Strain Analysis for Reconfigurable Silicon Nanowire Devices
    BUKOVSKý, Sayanti, BALDAUF, Tim, VAN DORP, Willem F., LöFFLER, Markus, TROMMER, Jens, HEINZIG, André, WEBER, Walter M., MüHLE, Uwe, MIKOLAJICK, Thomas, ZSCHECH, Ehrenfried, 2015. Strain Analysis for Reconfigurable Silicon Nanowire Devices. Microscience Microscopy Congress, UK, Manchester.
  • Functionality-enhanced logic gate design enabled by symmetrical reconfigurable silicon nanowire transistors
    J. Trommer, A. Heinzig, T. Baldauf, S. Slesazeck, T. Mikolajick, und W.M. Weber, 2015. Functionality-enhanced logic gate design enabled by symmetrical reconfigurable silicon nanowire transistors. IEEE Transactions on Nanotechnology, vol. 14(4), pp. 689-698. DOI: 10.1109/TNANO.2015.2429893
  • Effect of independently sized gates on the delay of reconfigurable silicon nanowire transistor based circuits
    TROMMER, Jens, SLESAZECK, Stefan, WEBER, Walter M., HEINZIG, André, BALDAUF, Tim, MIKOLAJICK, Thomas, 2015. Effect of independently sized gates on the delay of reconfigurable silicon nanowire transistor based circuits. EUROSOI-ULIS, pp. 17-20. DOI: 10.1109/ULIS.2015.7063762
  • Entwicklung von energieeffizienten Hochleistungstransistoren
    HERRMANN, Tom, FLACHOWSKY, Stefan, ILLGEN, Ralf, KLIX, Wilfried, STENZEL, Roland, 2012. Entwicklung von energieeffizienten Hochleistungstransistoren. Hochschulzeitschrift WISSEND, Hochschule für Wirtschaft und Technik Dresden, Nr. 2, S. 20 – 23.
  • Strained Isolation Oxide as Novel Overall Stress Element for Tri-Gate Transistors of 22nm CMOS and Beyond
    WEI, Andy , HERRMANN, Tom, FLACHOWSKY, Stefan, ILLGEN, Ralf, HöNTSCHEL, Jan, HORSTMANN, Manfred, KLIX, Wilfried, STENZEL, Roland, 2012. Strained Isolation Oxide as Novel Overall Stress Element for Tri-Gate Transistors of 22nm CMOS and Beyond. ISCDG 2012 – International Semiconductor Conference, Grenoble, Frankreich. DOI: 10.1109/ULIS.2016.7440037
  • Mobility and strain effects for <100> and <110> oriented silicon and SiGe transistor channels
    FLACHOWSKY, Stefan, HERRMANN, Tom, HöNTSCHEL, Jan, ILLGEN, Ralf, YANG ONG, Shiang, WIATR, Maciej, BALDAUF, Tim, KLIX, Wilfried, STENZEL, Roland, 2012. Mobility and strain effects for <100> and <110> oriented silicon and SiGe transistor channels. 2012 13th International Conference on Ultimate Integration on Silicon (ULIS),Grenoble, France, 06.03.-07.2012, pp. 5-8. DOI: 10.1109/ULIS.2012.6193343
  • Study of 22/20nm tri-gate transistors compatible in a low-cost hybrid FinFET/planar CMOS process
    T. Baldauf, A. Wei, R. Illgen, S. Flachowsky, T. Herrmann, J. Höntschel, M. Horstmann, W. Klix, R. Stenzel, 2012. Study of 22/20nm tri-gate transistors compatible in a low-cost hybrid FinFET/planar CMOS process. International Semiconductor Device Research Symposium 2011, Maryland, Proceedings, 07.12.-09.12.2011, Paper WP 11-09-04. DOI: 10.1109/ISDRS.2011.6135350
  • Strained isolation oxide as novel overall stress element for Tri-Gate transistors of 22nm CMOS and beyond
    STENZEL, Roland, KLIX, Wilfried, WEI, Andy, ILLGEN, Ralf, FLACHOWSKY, Stefan, HERRMANN, Tom, HöNTSCHEL, Jan, HORSTMANN, Manfred, 2012. Strained isolation oxide as novel overall stress element for Tri-Gate transistors of 22nm CMOS and beyond. IEEE Int. Semiconductor Conference Dresden - Grenoble 2012 (ISCDG), Proceedings, Session B.2.
  • Study of 22/20nm Tri-Gate Transistors Compartible in a Low-Cost Hybrid FinFET/Planar CMOS Process
    WEI, Andy, HERRMANN, Tom, FLACHOWSKY, Stefan, ILLGEN, Ralf, HöNTSCHEL, Jan, HORSTMANN, Manfred, KLIX, Wilfried, STENZEL, Roland, 2011. Study of 22/20nm Tri-Gate Transistors Compartible in a Low-Cost Hybrid FinFET/Planar CMOS Process. SDRS 2011 – International Semiconductor Device Research Symposium, College Park, USA. DOI: 10.1109/ISDRS.2011.6135350
  • Suppression of the corner effects in a 22 nm hybrid tri-gate/planar process
    WEI , Andy, HERRMANN, Tom, FLACHOWSKY, Stefan, ILLGEN, Ralf, HöNTSCHEL, Jan, HORSTMANN, Manfred, KLIX, Wilfried, STENZEL, Roland, 2011. Suppression of the corner effects in a 22 nm hybrid tri-gate/planar process. IEEE Int. Semiconductor Conference Dresden 2011, 27.09.-28.09. 2011, Proceedings, Paper 1.24. DOI: 10.1109/SCD.2011.6068714
  • Suppression of the Corner Effects in a 22 nm Hybrid Tri-Gate/Planar Process
    WEI, Andy, HERRMANN, Tom, FLACHOWSKY, Stefan, ILLGEN, Ralf, HöNTSCHEL, Jan, HORSTMANN, Manfred, KLIX, Wilfried, STENZEL, Roland, 2011. Suppression of the Corner Effects in a 22 nm Hybrid Tri-Gate/Planar Process. SCD 2011 – Semiconductor Conference, Dresden, Deutschland. DOI: 10.1109/SCD.2011.6068714
  • Simulation and Optimization of Tri-Gates in a 22nm Hybrid Tri-Gate/Planar Process
    WEI, Andy, ILLGEN, Ralf, FLACHOWSKY, Stefan , HERRMANN, Tom, FEUDEL, Thomas, HöNTSCHEL, Jan, HORSTMANN, Manfred, KLIX, Wilfried, STENZEL, Roland, 2011. Simulation and Optimization of Tri-Gates in a 22nm Hybrid Tri-Gate/Planar Process. ULIS 2011 – International Conference on Ultimate Integration of Silicon, Cork, Irland. DOI: 10.1109/ULIS.2011.5757974
  • Simulation and optimization of tri-gates in a 22 nm hybrid tri-gate/planar process
    WEI, Andy, ILLGEN, Ralf, FLACHOWSKY, Stefan, HERRMANN, Tom, FEUDEL, Thomas, HöNTSCHEL, Jan, HORSTMANN, Manfred, KLIX, Wilfried, STENZEL, Roland, 2011. Simulation and optimization of tri-gates in a 22 nm hybrid tri-gate/planar process. 12th International Conference on Ultimate Integration on Silicon, ULIS 2011, Cork, Proceedings, pp.3 - 6. DOI: 10.1109/ULIS.2011.5757974
  • Optimization of Stressor Overlayer Parameters for MOSFET's in "Cool Silicon" – Technologies
    ILLGEN, Ralf, FLACHOWSKY, Stefan, HERRMANN, Tom, FEUDEL , Thomas, HöNTSCHEL, Jan, HORSTMANN, Manfred, KLIX, Wilfried, STENZEL, Roland, 2010. Optimization of Stressor Overlayer Parameters for MOSFET's in "Cool Silicon" – Technologies. Nanofair – 8th International Nanotechnology Symposium, Dresden, Deutschland.
  • Analyse und Optimierung von verspannten Schichten auf CMOS–Transistoren
    ILLGEN, Ralf, FLACHOWSKY, Stefan, HERRMANN, Tom, FEUDEL, Thomas , HöNTSCHEL, Jan, HORSTMANN, Manfred, KLIX, Wilfried, STENZEL, Roland, 2010. Analyse und Optimierung von verspannten Schichten auf CMOS–Transistoren. 11. Nachwuchswissenschaftlerkonferenz, FH Schmalkalden, Deutschland; Tagungsband S. 181-186.
  • Stress Memorization Technique for n-MOSFETs: Where is the Stress Memorized?
    S. Flachowsky, R. Illgen, T. Herrmann, T. Baldauf, A. Wei, J. Höntschel, W. Klix, R. Stenzel und M. Horstmann, 2010. Stress Memorization Technique for n-MOSFETs: Where is the Stress Memorized?. 11th International Conference on Ultimate Integration on Silicon, Glasgow, Schottland, Tagungsband S. 149–152.
  • Optimization of stressor overlayer parameters for MOSFETs in „Cool Silicon“ – Technologies.
    ILLGEN, Ralf, FLACHOWSKY, Stefan, HERRMANN, Tom, FEUDEL, Thomas, HöNTSCHEL, Jan, HORSTMANN, Manfred, KLIX, Wilfried, STENZEL, Roland, 2010. Optimization of stressor overlayer parameters for MOSFETs in „Cool Silicon“ – Technologies.. 8th International Nanotechnology Symposium, Dresden, 06.07-07.07.2010.
  • Stress memorization technique for n-MOSFETs: Where is the stress?
    Flachowsky, S.; Illgen, R.; Herrmann, T.; Baldauf,T.; Wei, A.; Höntschel, J.; Klix, W.; Stenzel, R.; Horstmann, M.:, 2010. Stress memorization technique for n-MOSFETs: Where is the stress?. 11th International Conference on Ultimate Integration of Silicon (ULIS), Glasgow, 17.03. - 19.03.2010.